Ethernet in Design (100Gb/s Lane Rate)

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Ethernet in Design (100Gb/s Lane Rate)

Date: Wednesday, June 7

Time: 10am PT/1pm ET

Duration: 90 minutes

Registration link:

Abstract: The next generation of Ethernet has been defined with the recently published IEEE 802.3ck standard based on 100Gb/s lane rates (PAM4 signaling at 53 GBd).  This panel of Ethernet Alliance members will provide an overview of this new standard, reviewing some of the key content, changes from previous technologies, as well as highlighting some of the challenging aspects of the design.  Additionally the session will include demonstration results of Ethernet variants at 53 GBd i.e. 100 Gb/s per lane showing BER performance, FEC statistics, packet tests over different media types such as backplane, DAC and optical fiber.

Lastly, this panel also includes a discussion of the recent plugfest that Ethernet Alliance members held where 100Gbps per lane signaling was tested with some of the member benefits from participation.

Moderator: Kae Dube Ethernet Operations Manager·UNH InterOperability Lab

Panelist: John Calvin Senior Strategic Planner IP Wireline Solutions·Keysight Technologies

Panelist: Adithya Muralidharan Staff Application Engineer·Intel

Panelist: Nathan Tracy Technologist, System Architecture Team and Manager of Industry Standards·TE Connectivity

Panelist: Pavel Zivny System Engineer and Domain Expert for High Speed Serial Data Oscilloscopes·Tektronix