TEF 2025 – Day 1 Agenda

Keynote Presentation – “Transitioning to 400G SerDes: Key Drivers and System Design Implications for Future AI Workloads”

Presenter: Halil Cirit, AI Interconnect Architect, Meta

“XPUs and the Future of AI Connectivity”

Presenter: Baron Fung, Dell’Oro

“400 Gb/s Signaling for AI Networks From a System Perspective”

Join us as industry experts share their viewpoints on AI system definition, based on 400 Gb/s signaling

Moderator: Alan Weckel, 650 Group

Participants:

• • Gary Nicholl, Cisco, “CMIS – The management interface that ties everything together for AI”
  • TBD, Cisco, “Building systems for AI deployments”
  • Arihant Jain, Arista, “AI Scale-Out Network Designs and Interconnects”

Ultra Ethernet: AI Evolution & Insights for 400G

Adee Ran, Cisco

“The Path To 448G in Support of Next Generation AI”

Join us as the OIF gives an update on its 448 Framework

Moderator: Nathan Tracy, OIF Board Member, TE Connectivity

Participants:

• • Cathy Liu, Broadcom, “Electrical Interconnect Considerations”
  • Mike Li, Altera (an Intel Company”, “Electrical Channel and Modulation Considerations”
  • Jeff Hutchins, Ranovus, “Does Optics Have What Is Needed For Scale-Up/Out Links?”
  • John Calvin, Keysight Technologies, “Advances in Measurement Science”

“FEC and 400 Gb/s Signaling for AI Networks”

FEC will play a pivotal role in determining 400 Gb/s signaling.  This panel will explore this topic and its interaction with modulation.

Moderator: Alan Weckel, 650 Group

Participants:

• • Xiang He, Huawei, “FEC for 448G: Can Today’s FEC Survive Tomorrow’s Modulation?”
  • Tony Chan Carusone, Alphawave Semi, “Channel-Aware Modulation and FEC Selection for 400G+ Ethernet”
  • Adam Healey, Broadcom, “Benefits and limitations of inner error-correcting codes for 400 Gb/s per lane electrical links”