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TEF 2025 – Day 2 Agenda

The Ethernet Alliance will be hosting their next Technology Exploration Forum “Ethernet for AI” in Mountain View, CA on December 2-3, 2025. The agenda for this event is outlined below. To register, click here.

To view the Day 1 agenda, click here.

Wednesday, December 3, 2025
Time Title
9:00 AM Opening Comments – John D’Ambrosia, Ethernet Alliance TEF Event Chair
9:05 AM

“400 Gb/s Optics for AI Networks”

Join us as industry experts share their viewpoints on the role of optical solutions for future AI systems, based on 400 Gb/s signaling

Moderator: Vlad Kozlov, LightCounting

Participants:

    • Gilad Shainer, Nvidia, “Co-Packaged Silicon Photonics Switches for Gigawatt AI Factories”
    • Jose Castro, Panduit, “Enabling Massive Scale-Out AI Networks with Ethernet and Optical Lane Breakouts”
    • Dr. Naim Ben-Hamida, Ciena, “Ethernet for AI”
10:35 AM Break
10:45 AM

“Copper Interconnect for 400 Gb/s Signaling for AI Networks”

This panel of industry experts will explore copper interconnect for 400 Gb/s signaling to support future AI systems.

Moderator: Lisa Huff, DC Tech Analysis

Participants:

    • Kasthuri Sankar Damodharan, Amphenol, “Solving 400Gb/s at the Speed of Interconnect”
    • Ashika Pandankeril Shaji, TE Connectivity, “400G/lane Interconnects for AI: Channel Feasibility, Reach Extension, and Early Measurement Results”
    • Augusto Panella, Molex, “Copper Backplane Considerations for 400G Signaling”
12:00 PM Lunch
1:00 PM

SNIA Storage for AI Efforts

Tom Palkert, Samtec, Chair of the SNIA/SFF Transceivers Subgroup
1:20 PM

“400 Gb/s Electrical Signaling for AI Networks”

This panel of industry experts will explore topics related to 400 Gb/s electrical signaling for AI Networks.

Moderator: Lisa Huff, DC Tech Analysis

Participants:

    • Ayal Shoval, Synopsys, “Proposed Enhancements to COM: Addressing RLM Sensitivity in Next-Generation Ethernet Designs”
    • Hadrien Louchet, Keysight, “Advancing 448G Signal Generation and Analysis with Modern Test & Measurement Solutions”
    • Jim Hsieh, MediaTek, “Unveiling Bottlenecks in Measured Co-Packaged Copper Channels: Sensitivity Analysis at 75–90 GBd for PAM6/8”
    • Bijan Nowroozi, Lightmatter, “Modularity at the Package Edge: Composable Interconnect for 400 Gb/s/Lane AI Systems”
2:50 PM Break
3:15 PM

“”Ethernet for AI Isn’t Just Evolving — It’s Exploding

Presenter: John D’Ambrosia, TEF Event Chair – IEEE 802.3 NEA “Ethernet for AI” Assessment (Futurewei)
3:50 PM

Defining 400bps per Lane Electrical and Optical Signaling for Ethernet

Presenter: Kent Lusted, Champion, IEEE 802.3 Mar 2026 CFI – 400Gbps Signaling Ethernet Project (Synopsys)
4:30PM Closing Comments, John D’Ambrosia – TEF Chair
4:45 PM End of Day