TEF 2025 – Day 2 Agenda

The Ethernet Alliance will be hosting their next Technology Exploration Forum “Ethernet for AI” in Mountain View, CA on December 2-3, 2025. The agenda for this event is outlined below. To register, click here.

To view the Day 1 agendaclick here.

Wednesday, December 3, 2025

Time Title
9:00 AM Opening Comments – John D’Ambrosia, Ethernet Alliance TEF Event Chair
9:05 AM

“400 Gb/s Optics for AI Networks”

Join us as industry experts share their viewpoints on the role of optical solutions for future AI systems, based on 400 Gb/s signaling

Moderator: Vlad Kozlov, LightCounting

Participants:

    • Gilad Shainer, Nvidia, “Co-Packaged Silicon Photonics Switches for Gigawatt AI Factories”
    • Jose Castro, Panduit, “Enabling Massive Scale-Out AI Networks with Ethernet and Optical Lane Breakouts”
    • Dr. Naim Ben-Hamida, Ciena, “Ethernet for AI”
    • Josh Elijah, Morgan Stanley, “Latency implications of layer 1 network infrastructure – The Future is Photonic!”
10:35 AM Break
10:45 AM

“Copper Interconnect for 400 Gb/s Signaling for AI Networks”

This panel of industry experts will explore copper interconnect for 400 Gb/s signaling to support future AI systems.

Moderator: Lisa Huff, DC Tech Analysis

Participants:

    • Sam Kocsis, Amphenol, “Solving 400Gb/s at the Speed of Interconnect”
    • Ashika Pandankeril Shaji, TE Connectivity, “400G/lane Interconnects for AI: Channel Feasibility, Reach Extension, and Early Measurement Results”
    • Augusto Panella, Molex, “Copper Backplane Considerations for 400G Signaling”
12:00 PM Lunch
1:00 PM

SNIA Storage for AI Efforts

Tom Palkert, Samtec, Chair of the SNIA/SFF Transceivers Subgroup

1:20 PM

“400 Gb/s Electrical Signaling for AI Networks”

Join us as the OIF gives an update on its 448 Framework

Moderator: Lisa Huff, DC Tech Analysis

Participants:

    • Ayal Shoval, Synopsys, “Proposed Enhancements to COM: Addressing RLM Sensitivity in Next-Generation Ethernet Designs”
    • Hadrien Louchet, Keysight, “Advancing 448G Signal Generation and Analysis with Modern Test & Measurement Solutions”
    • Jim Hsieh, MediaTek, “Unveiling Bottlenecks in Measured Co-Packaged Copper Channels: Sensitivity Analysis at 75–90 GBd for PAM6/8”
    • Bijan Nowroozi, Lightmatter, “Modularity at the Package Edge: Composable Interconnect for 400 Gb/s/Lane AI Systems”
2:50 PM Break
3:15 PM

“”Ethernet for AI Isn’t Just Evolving — It’s Exploding: Kicking off 400G/lane and 3.2TbE in 2026!””

AI is the next driver of Ethernet.  Join leaders of the IEEE 802.3 Ethernet Community in exploring the start of Ethernet’s development to address AI’s need for 400 Gb/s per lane and 3.2 Tb/s Ethernet.

Moderator: David Law, HPE, Chair, IEEE 802.3 Ethernet Working Group

Participants:

    • Kent Lusted, Synopsys, “Defining 400 Gb/s Electrical Signaling for Ethernet”
    • Mark Nowell, Cisco, “Defining 400 Gb/s Optical Signaling for Ethernet”
    • John D’Ambrosia, Futurewei Technologies, “Defining 3.2 Tb/s Ethernet”
4:30PM Closing Comments, John D’Ambrosia – TEF Chair
4:45 PM End of Day