Ethernet’s AI Evolution

The IEEE P802.3dj project is defining the underlying 200Gb/s PAM4 signaling technologies in support of chip-to-chip, chip-to-module, backplane, copper cable, and single-mode fiber technologies to facilitate the numerous specifications for 200GbE, 400GbE, 800GbE, and 1.6TbE. These efforts are expected to be completed in the second half of 2026 so AI applications will have some near-term solutions to leverage. However, the staggering growth rates of computational power require the industry to start looking beyond 200 Gb/s based signaling now for the networks of the future.

To address this topic, the Ethernet Alliance recently hosted a two-day TEF event, entitled “Ethernet in the Age of AI.” This Ethernet Alliance event brought together industry experts and key players from different organizations to explore how Ethernet may evolve in the future to support the high-performance requirements of the different networks used to facilitate AI applications.  Industry experts and participants in IEEE 802.3, the Ultra Ethernet Consortium (UEC), the Open Compute Project (OCP), the Storage Networking Industry Association (SNIA), and the Optical Internetworking Forum (OIF), as well as keynote speeches from Ram Huggahalli of Microsoft, Moray McLaren of Google, and Nicolaas Viljoen of Meta, combined to give the event simultaneous top-down and bottom-up perspectives that proved insightful.

One of the outcomes of this event was the realization the development of 400 Gb/s signaling would be an industry-wide problem. It wasn’t solely an application, network, component, or interconnect problem. Overcoming the challenges to support 400 Gb/s signaling will likely require all the tools available for each of the various layers and components.

Kudos to the Ethernet Alliance for taking the lead and initiating these collaborative industry discussions. Other events are already being discussed for 2025, such as the SNIA / SFF 400G AI Workshop for January 27, 2025 (see https://www.eventcreate.com/e/aiworkshopbysniasff), and the Ethernet Alliance is preparing another TEF to re-visit this topic later this year.   Additionally, at its January 2025 Interim, the IEEE 802.3’s New Ethernet Applications (NEA) Ad hoc will discuss initiation of an assessment to explore Ethernet electrical and optical interconnects for AI front-end, scale-up and scale-out networks, based on greater than 200 Gb/s lane rates, to address next generation AI applications.

To further assist the industry as it begins these discussions, the Ethernet Alliance is making the proceedings (keynotes and panel presentations) of its 2024 TEF event available at https://ethernetalliance.org/tef-2024-ethernet-in-the-age-of-ai-presentations-form/.

Thanks to all the individuals and organizations making these contributions, they will serve as part of Ethernet’s continuing evolution.