Halil Cirit – Meta
Bio: Halil Cirit is a Highspeed SerDes and Systems Architect for AI/HPC systems at Meta. In his previous roles, he has architected and designed various blocks for PCIE, GDDR, 10G, 25G, 50G, and 100G Ethernet SerDes at NVIDIA, Broadcom, and Inphi.
Presentation Abstract: Ever increasing demand for faster and faster communication has forced SERDES data rates to increase in two folds in every generation for two decades. With the increasing importance of AI, requirement for higher data rate inter-processor or processor-memory communications putting even more pressure for next generation SERDES solution. On the other hand, electronic component bandwidths are not scaling well with the recent silicon technologies and improving SNR is also quite challenging. We are expecting some improvements BW and SNR figures, but remaining gap should be filled with higher performance signal processing and FEC.
Higher performance signal processing and FEC means, operation closer to the channel capacity at a lower Eb/No, where raw bit error rate is higher. Legacy methods will struggle in these levels. Furthermore, sequential nature of those methods also requires costly unrolling to operate at required line rates. Possible parallel demodulation strategies with no error propagation might be very attractive for low complexity and low delay (no or smaller interleaver) implementations. However, such an approach will require dual implementation for backward compatibility.
From FEC perspective, it is possible to extend KP4 for longer block lengths with similar inner codes for slightly better performance if current demodulator structures are preserved. For more improvement, longer interleaver can be an option. There are also very attractive alternatives if error propagation can be minimized. Polar codes can be a good example for such alternatives. There are soft decision polar decoder studies operating above 1TB/s that a can achieve better than 1pJ/b energy efficiency in 16nm technology node. It is possible to operate new generation codes, utilizing soft decision decoding algorithms, with better performance and better energy efficiency with respect to existing KP4 or its descendants.
In our presentation we will try to review current implementation challenges to achieve 400Gb/s throughput per pin and we will focus on a possible polar code implantation that can provide significant performance improvement without additional overhead, delay or power dissipation.
