Mike Li – OIF Board Member (Intel)

By Ethernet Alliance

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Bio: Peng (Mike) Li is an Intel Fellow and the Chief Technologist on SerDes, high-speed I/O (HSIO), and interconnects/platforms at Intel PSG/Atera, co-driving/leading Intel/Altera SerDes, HSIO, and interconnect/platforms strategy and roadmap, as well as industry standards, SerDes and HSIO architecture; electrical and optical signaling, silicon photonics integration; and optical field-programmable gate arrays (OFPGAs). Li joined Intel in 2015 with the acquisition of Altera Corp., where he had held a similar role as an Altera Fellow since 2012.

A distinguished scientist and technologist, Li has contributed extensively to industry standards during his career, including PCI Express, Ethernet/Ultra Ethernet (UEC), Optical Internetworking Forum (OIF), Fibre Channel (FC), Serial ATA (SATA), and JEDEC. He has authored/co-authored 5 books, book chapters, book sections on jitter and SerDes and HSIO. He has published widely, including 140+ papers and 40+ patents on high-speed circuits and systems, modeling, simulation, and test and measurement, and high-energy astrophysics.

Li earned a bachelor’s degree in space physics from the University of Science and Technology of China in Hefei, China; a master’s degree in physics and a Master’s Degree in electrical and computer engineering, and a Ph.D. in physics from the University of Alabama in Huntsville (UAH). Li was named an IEEE Fellow in 2012, an Intel Fellow in 2015, and Engineer of the year (2018, Designcon). He was an Affiliated Professor with the Department of Electrical Engineering, University of Washington, Seattle, 2010-2020.

Presentation Abstract: This presentation will first review how has the industry developed Electrical I/O technologies and standards (i.e., common electrical interface (CEI)) for the current 224 Gbps-PAM4 generation, from the previous 112 Gbps-PAM4 generation. Then it will highlight some of the key market requirements and associated technical challenges for the next generation 448 Gbps electrical I/O, and review a few technology options/paths that could meet the requirements and overcome the challenges.

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