Adee Ran – Cisco

Bio: Adee Ran has been an active contributor to the IEEE 802.3 Standard for Ethernet since 2008 and is currently serving as the lead electrical track editor for the IEEE P802.3dj task force. Prior to this role, he has held key technical and editorial positions in several IEEE 802.3 task forces.

Adee earned both BSc and MSc degrees in Electrical Engineering from the Technion, Israel Institute of Technology. With a professional career spanning over 30 years, he has dedicated more than two decades to the development, architecture, research, standardization, and mentoring of Ethernet technology, initially at Intel Corporation, and subsequently at Cisco Systems.

Adee is a Principal Engineer at Cisco Systems and a Senior Member of the IEEE. In addition to his activity in IEEE standards, Adee also co-chairs the Physical Layer Working Group in the Ultra Ethernet Consortium. Adee has authored several conference papers and holds numerous patents in the field of Ethernet technology.

Presentation Abstract:  Over the past two decades, Ethernet data rates have grown exponentially from 10 Gb/s (802.3ap) to 800 Gb/s (802.3df), utilizing advanced electrical signaling over differential pairs. Currently, the development of 200 Gb/s per lane electrical signaling specifications is underway in IEEE P802.3dj. This evolution has incorporated a range of sophisticated techniques such as DSPs, multi-lane striping, error correction codes, PAM4 signaling, link training, and most recently, maximum-likelihood sequence detection (MLSD). These innovations have generally maintained compatibility with signaling over optical media, enabling diverse modular implementations and backward compatibility.

At 200 Gb/s, these techniques may be nearing the limit of their effectiveness, and the diminishing reach of electrical signaling may become an issue for future deployment of large-scale AI networks. While coherent communication is revolutionizing optical signaling, similar innovations are necessary for the future of electrical signaling.

In this presentation, we will explore some outside-the-box strategies for next-generation Ethernet, along with the inherent tradeoffs of each approach. We aim to chart potential paths for the continued evolution of Ethernet as the physical layer of choice for AI networks, balancing performance gains with practical constraints.