Sam Johnson – Intel
Bio: Sam Johnson is an Engineering Manager with Intel Corporation, leading the Link Applications Engineering team within the Network and Edge Group. Sam started at Intel in 2010 with a focus on 10G Serial Ethernet debug and has built a career based on High Speed Serial Ethernet PHY and pluggable media behavior, configuration and interoperability. He and his team work to define and develop the Ethernet hardware control infrastructure and to enable and support Intel customer Ethernet solutions. Sam holds multiple patents related to Ethernet interoperability, and is a co-chair of the High Speed Networking subcommittee within the Ethernet Alliance with a focus on L1 protocol and interoperability testing. Outside of work, Sam enjoys spending time with his family, woodworking, and all forms of outdoor recreation.
Presentation Abstract: Interoperability and the reliable establishment of a robust data connection between devices is a key foundation of a healthy Ethernet ecosystem and a fundamental driver of the burden to support a product. Specification compliance is a core requirement of healthy interoperability and ease of product integration, but early to market devices with targeted use cases focus on functionality regardless of specification compliance or completeness. This can cause significant interop issues as more devices enter the market and are expected to function with incumbent products that may or may not comply with the final version of a published specification.
Other challenges to reliable interoperability are the growing complexity of Ethernet protocols as we strive to achieve higher and higher speeds and the rapidly expanding landscape of pluggable modules. New types of cables and media such as active electrical cables (AEC), linear pluggable optics (LPO) and half-retimed (a.k.a TRO/RTLR) optical modules look to solve key technical challenges of lowering power and/or extending channel reach, but make the goal of open interoperability much harder to achieve.
Interoperability depends on more than just electrical conformance and requires both devices to implement a compatible wholistic solution covering the system, media, firmware, PHY and link management. These components must work seamlessly together to establish the reliable network that is expected of Ethernet. As Ethernet emerges as the fabric of AI and we look to future signaling speeds such as 400 Gbps/lane, maintaining interoperability will remain one of the key challenges to implementors and standards bodies. This presentation will explore these challenges and the industry wide testing efforts occurring to resolve them.
